Effects of trapped charges on Hg-Schottky capacitance-voltage measurementsof n-type epitaxial silicon wafers

The effects of surface charge in the oxide layer for Hg-Schottky capacitanc e-voltage (C-V) measurements have been discussed in detail. The accumulatio n of majority carriers at the Si surface has been identified as a major fac tor controlling the stability and accuracy of the Hg-Schottky C-V measureme nt. For n-type wafers, the fixed oxide charge in Si oxide layer induces ele ctron accumulation at the oxide/Si interface. This electron accumulation ca nnot be dissipated until a depleting voltage as high as -5.0 V is applied d epending on the preparation of the oxide layer. II has been found that intr oducing Cu during the growth of the oxide layer can produce a deep trap lev el in the oxide. Pre-electrical-held stress at 5 MV/cm for 5 s can fill the se traps and eliminate electron accumulation, resulting in a stable and acc urate C-V measurement. Our results on p-type wafers show that the fixed oxi de charge in the oxide layer can establish a surface depletion condition an d produce a stable and accurate C-V measurement. With these experimental re sults, we propose that Si oxide layer can improve the stability and accurac y of the Hg-Schottky C-V measurement for both n- and p-type wafers. For n-t ype wafers, pre-electrical stress and a Si oxide layer with deep electron t rap level are necessary; for p-type wafers, only the fixed oxide charge is needed. (C) 2000 American Vacuum Society. [S0734-2101(00)02404-0].