C++ based system simulator for pre-verification of system-on-a-chip devices

In this paper, we will present our C++ based system simulator called "Class Mate" Tor use in both software and architecture pre-verification. It is esp ecially designed for use in system-on-a-chip devices. Our approach is that of using a C++ class-based modeling technique in order to describe hardware modules, where an abstracted bus technology is newly proposed to connect I /O components to the system. Also, our approach allows for non cycle-accura te modeling technology for target hardware in order to improve simulation s peed, and reduce the coding time. Moreover, this simulator can be used in c onjunction with the behavioral synthesizer called "Cyber," where it automat ically generates the C++ cycle/bit accurate model for ClassMate from the al gorithmic C-language source. This function allows the user to build up a co -simulation environment which involves automatically generated C++ hardware models and pre-implemented ISS-based CPU models. In this system, applicati on software can be systematically debugged. We will show how this methodolo gy achieves a high performance and more flexibility for system on a chip.