Incorporating yield enhancement into the floorplanning process

The traditional goals of the floorplanning process for a new integrated cir cuit have been minimizing the total chip area and reducing the routing cost , i.e., the total length of the interconnecting wires. Recently, it has bee n shown that, for certain types of chips, the floorplan can affect the yiel d of the chip as well. Consequently, it becomes desirable to consider the e xpected yield, in addition to the cost of routing, when selecting a floorpl an. The goal of this paper is to investigate the two seemingly unrelated, a nd often conflicting, objectives of yield enhancement and routing complexit y minimization. We analyze the possible trade-offs between the two and then present a constructive algorithm for incorporating yield enhancement as a secondary objective into the floorplanning process, with the main objective still being the minimization of the overall routing costs.