Fault-tolerant processor arrays based on the 11/2-track switches with flexible spare distributions

A mesh-connected processor array consists of many similar processing elemen ts (PEs) which can be executed in both parallel and pipeline processing. Fa r the implementation of an array of large numbers of processors. some fault -tolerant issues are necessary to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we propose a fault-tolerant reco nfigurable processor array using single-track switches like Kung et al.'s m odel in [1]. The reconfiguration process in our model is executed based on the concept of the "compensation path" like Kung et al.'s method, too. In o ur model, spare PEs are not necessarily put around the array, but are more flexibly put in the array by changing connections between spare PEs and non spare PEs white retaining the connections among nonspare PEs in the same ma nner in Kung et al.'s model. The proposed model has such a desirable proper ty that physical distances between logically adjacent PEs in the reconfigur ed array are within a constant, that is, independent of sizes of arrays. We show that the hardware overhead of the proposed model is a little greater than that of Kung et al.'s model, while the yield of the proposed model is much better than that of Kung et al.'s model.