Procedures for static compaction of test sequences for synchronous sequential circuits

We propose three static compaction techniques for test sequences of synchro nous sequential circuits. We apply the proposed techniques to test sequence s generated for benchmark circuits by various test generation procedures. T he results show that the test sequences generated by all the test generatio n procedures considered can be significantly compacted. The compacted seque nces thus have shorter test application times and smaller memory requiremen ts. As a by-product, the fault coverage is sometimes increased as well. Add itionally, the ability to significantly reduce the length of the test seque nces indicates that it may be possible to reduce test generation time if su perfluous input vectors are not generated.