System architecture and hardware design of the CDF XFT online track processor

A trigger track processor is being designed for CDF Run 2. This processor i dentifies high momentum (P-T > 1.5 GeV/c) charged tracks in the new central outer tracking chamber for the CDF II detector. The design of the track pr ocessor, called the eXtremely Fast Tracker (XFT), is highly parallel and ha ndle an input rate of 183 Gbits/sec and output rate of 44 Gbits/sec. The XF T is pipelined and reports the results for a new event every 132ns. The XFT uses three stages, hit classification, segment finding, and segment linkin g. The pattern recognition algorithms for the three stages are implemented in Programmable Logic Devices (PLDs) which allow for in-situ modification o f the algorithm at any time. The PLDs reside on three different types of mo dules. Prototypes of each of these modules have been designed and built, an d are working. An overview of the hardware design and the system architectu re are presented.