Dark-field phase shifter edge mask for actual logic gate patterns

The fabrication of a dark-field phase shifter edge mask that improved the l ithography process latitude for fine transistor gate patterns was examined. The applicability of this mask was confirmed by analyzing of phase shift m ask fabrication yield. The pattern formation method used both a dark-field phase shifter edge mask and a clear-field binary mask. It was clarified tha t the fabrication yield of the phase shifter edge mask was dependent on the transparent area of the phase shifter region. Clear-field phase shifter ed ge masks were fabricated with difficulty because of shifter defects. On the other hand, the fabrication yield of the dark-field phase shifter edge mas k was about two times that of the clear-field phase shifter edge mask. This mask was applied to an actual logic device. Resist patterns were fabricate d with a line width accuracy of 0.15 +/- 0.01 mu m and a focus budget of +/ - 0.4 mu m. The dark-field phase shift mask exposure method also improved t he lithography process latitude significantly.