A review of high-level synthesis for dynamically reconfigurable FPGAs

Dynamically Reconfigurable Field Programmable Gate Arrays (DR FPGAs) change many of the basic assumptions of what hardware is. DR FPGA-based dynamical ly reconfigurable computing has become a powerful methodology for achieving high performance while minimizing the resource required in the implementat ion of many applications. The key to harnessing the power of DR FPGAs for m ost applications is to develop high-level synthesis tools for transforming automatically an algorithmic level behavioral specification into DR FPGA co nfigurations. In this paper we survey the current state-of-the-art in high- level synthesis techniques for dynamically reconfigurable systems. The diff erences in high-level synthesis technology between classical systems and dy namically reconfigurable systems are discussed. Then, we describe the basic tasks in the high-level synthesis of dynamically reconfigurable systems. F inally, techniques that have been developed in the past few years for the h igh-level synthesis of dynamically reconfigurable systems are presented. (C ) 2000 Elsevier Science B.V. All rights reserved.