Distributed ESD protection for high-speed integrated circuits

Conventional ESD guidelines dictate a large protection device close to the pad. The resulting capacitive load causes a severe impedance mismatch and b andwidth degradation. A distributed ESD protection scheme is proposed to en able a low-loss impedance-matched transition from the package to the chip. A simple resistive model adequately predicts the ESD behavior under stress according to the charged device and human body models, The large area of th e distributed ESD scheme would limit its application to designs such as dis tributed amplifiers, rf transceivers, A/D converters, and serial links with only a few dedicated high-speed interfaces. The distributed ESD protection is compatible with high-speed layout guidelines, requiring only low-loss t ransmission lines in addition to a conventional ESD device.