A digital implementation of a frequency steered phase locked loop

A digital implementation of a new technique that delivers an extremely accu rate and stable phase locked loop system (PLL) is presented. The new techni que uses competing phase and frequency loops to incorporate an accurate loc al reference frequency into the phase locked loop structure. Disturbances o n the phase loop caused by the digital frequency loop are identified and a method to mitigate the disturbances is developed, The implementation is pri marily designed for high-speed clock and data recovery and experimental res ults from a clock recovery system for nonreturn to zero data streams at 155 .52 MHz are presented.