Super thin-film transistor with SOICMOS performance formed by a novel grain enhancement method

High performance super TFT's with different channel widths and lengths, for med bg a novel grain enhancement method, are reported. High temperature ann ealing has been utilized to enhance the polysilicon grain and improve the q uality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device sealing, it is possible to fabricate the entire trans istor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been stu died? indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump a nd early punchthrough of wide devices. The probability for the channel regi on of a TFT to cover multiple grains decrease significantly when the del ic e is scaled down, resulting in better device performance and higher uniform ity.