An adiabatic 4 : 2 compressor design for low power VLSI

4:2 compressors are basic components ill the design of parallel multipliers . Low power consuming 4:2 compressors can result in a significant reduction of power when realizing power-efficient multipliers in any low power orien ted systems. In the area of low power integrated circuit design, adiabatic switching technique has received considerable attention in the recent years . Many adiabatic logic architectures have been reported. In this letter, a low power 4:2 compressor circuit based on the adiabatic switching principle is proposed. When simulated using HSPICE, it was shown that the proposed c ircuit consumed very much less gower than the static CMOS version.