Novel extension of neu-MOS techniques to neu-GaAs

The neuron-MOS (neu-MOS) transistor, recently discovered by Shibata and Ohm i in 1991 [T. Shibata, T. Ohmi, International Electron Devices Meeting, Tec hnical Digest, 1991] uses capacitively coupled inputs onto a floating gate. Neu-MOS enables the design of conventional analog and digital integrated c ircuits with a significant reduction in transistor count [L.S.Y. Wong, C.Y. Kwok, G.A. Rigby, in: Proceedings of the 1997 IEEE Custom Integrated Circu its Conference, 1997; B. Gonzales, D. Abbott, S.F. Al-Sarawi, A. Hernandez, J. Garcia, J. Lopez, in: Proceedings of the XIII Design of Circuits and In tegrated Systems Conference (DCIS'98), 1998, pp. 62-66]. Furthermore, neu-M OS circuit characteristics are relatively insensitive to transistor paramet er variations inherent in all MOS fabrication processes. Neu-MOS circuit ch aracteristics depend primarily on the floating gate coupling capacitor rati os. It is also thought that this enhancement in the functionality of the tr ansistor, i.e. at the most elemental level in circuits, introduces a degree of flexibility that may lead to the realisation of intelligent functions a t a system level [T. Ohmi, T. Shibata, in: Proceedings of the 20th Internat ional Conference on Microelectronics, vol. 1, 1995, pp. 11-18]. This paper extends the neu-MOS paradigm to complementary gallium arsenide based on HIG FET transistors. The design and HSPICE simulation results of a neu-GaAs rip ple carry adder are presented, demonstrating the potential for very signifi cant transistor count and area reduction through the use of neu-GaAs in VLS I design. Preliminary simulations indicate a reduction of a factor of four in transistor count for the same power dissipation as conventional compleme ntary GaAs. The small gate leakage is shown to be useful in eliminating unw anted charge build-up on the floating gate. (C) 2000 Elsevier Science Ltd. All rights reserved.