On improving test quality of scan-based BIST

In this paper, we explore two techniques, under the existing scan-based bui lt-in self-test (BIST) architectures, for improving the test quality with p ractically no additional overhead. The proposed technique are an almost-ful l-scan BIST strategy and a general scan-based BIST test application scheme. We first demonstrate that under the scan-based BIST architecture, full sca n may not result in the highest fault coverage (FC) and unscanning a small number of scan flip-flops may increase the BIST FC. We then present an algo rithm for identifying those not-to-be-scanned flip-flops. We further show t hat the proposed general scan-based BIST test application scheme could also result in higher BIST FC and only requires a minor modification to the BIS T controller. Experiments have been conducted using an industrial tool, psb 2, on benchmark circuits to illustrate the effectiveness of the proposed te chniques and algorithms. The results have demonstrated that both techniques are able to maximize the FC and reduce the test application time without a dditional test hardware comparing to the conventional scan-based BIST archi tectures.