System-On-Chip: A way around lithography limitations

Traditionally, lithography has been the driving force behind the exponentia l growth rate of Microelectronics, thanks also to the easy scalability of M OS devices. Even if up to now every prophecy for a slow-down of the growth rate has been proven false, there appears to be a growing uncertainty about which lithography could be used to go below 0.1 mu m. However Microelectro nics is not limited to smaller feature size, especially in the era of Syste m-On-Chip integration. In this paper we would like to review the main facto rs which determine the performances of an integrated circuit and show how t he density of integration perceived by the final user can be increased, ind ependently from lithographic considerations.