Process development for 30 nm poly gate patterning on 1.2 nm oxide.

The evaluation of electrical performances of ultimate MOSFET requires litho graphy and etching of poly gate in the 30 nm range while gate oxide thickne ss is close to 1.2 nm. This paper describes the process developed for etchi ng of these ultra narrow gates. For oxide thickness lower than 2 nm, we poi nt out that resist mask has to be replaced by a hard mask to prevent oxide pitting or CD increasing due to slopped profile. We also show that the redu ction of photoresist features size is not a good option but it can be repla ced by a hard mask size reduction to achieve sub 50 nm poly features with a n average slope close to 87 degrees and no pitting of the 1.2 nm oxide unde r layer.