Minimizing thick resist sidewall slope dependence on design geometry by optimizing bake conditions

We successfully optimized the sidewall slope of a 2.5 mu m thick photoresis t. We found that the sidewall slope strongly depends on the pattern size an d thickness of the photoresist. By optimizing the hard-bake process conditi ons it was possible to minimize this sidewall dependence and therefore to i mprove the implant blocking capability at the resist corners. As a result o f this improvement we could obtain a higher process margin for the isolatio n spacing for CMOS inverter structures. We present simulation data which cl early show the impact of insufficient blocking capability on the final devi ce structure.