CURRENT-MODE CMOS-BASED DECODER WITH REDUNDANTLY REPRESENTED 0-ADDEND-METHOD FOR MULTIPLE-RADIX SIGNED-DIGIT NUMBER

We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In th is paper, a new decoding method with the selective summation of a redu ndantly represented addend ''0 = [-1 r]'' is proposed, where r is the radix and the addend is applied to each digit with a negative value an d any consecutively higher digit takes which has a value of 0. A newly designed literal linear circuit is realized, which has a current-swit ch function that makes independently the short path when each digit ha s a value of 0. Through the parallel connections of these current swit ches, the same addend signal at the lower digit is transmitted in a hi gher speed. The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the sele ctive summation of a redundantly represented 0 addend and the output r esults of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit s ize.