INSTRUCTION SEQUENCE BASED SYNTHESIS FOR APPLICATION-SPECIFIC MICROARCHITECTURE

In this paper, a systematic method which generates the micro-architect ure of Application Specific Instruction Processor (ASIP) is proposed. Different from previous works, the data path and control path are gene rated From the instruction sequence which is generated by translating the compiled assembly code. A graphical representation method called R egister Transfer Graph (RTG) is introduced to describe the micro-opera tions of instruction sequence. To achieve high performance, we perform micro-operation level scheduling which dynamically assigns the micro- operations of instruction sequence to the control steps. By transformi ng the architecture using synthesis parameters, design space is explor ed more extensively. Connection cost is minimized by removing the inef ficient data transfer paths.