Framework and tools for run-time reconfigurable designs

The paper describes a framework and tools for automating the production of designs that can be partially reconfigured at run time. The approach involv es several stages, including: (i) a partial evaluation stage, which produce s configuration files for a given design, where the number of configuration s is minimised during the compile-time sequencing stage; (ii) an incrementa l configuration calculation stage, which takes the output of the partial ev aluator and generates an initial configuration file and incremental configu ration files that partially update preceding configurations; and (iii) an o ptimisation stage for devices or systems supporting simultaneous configurat ion of multiple components. While many of the techniques are independent of the design language and device used, experimental tools have been develope d that target Xilinx 6200 devices. Simultaneous configuration, for example, can be used to reduce the time for reconfiguring an adder to a subtractor from time linear with respect to its size to constant time at best and loga rithmic time at worst. The tools have been used in developing a variety of designs, including arithmetic, video and database applications.