Power optimisation of FPGA-based designs without rewiring

A new technique is proposed to perform power-oriented reconfiguration of co mbinational circuits implemented using look-up table (LUT)-based FPGAs. The main features of this approach are: exploitation of functional flexibiliti es, concurrent optimisation of multiple LUTs based on Boolean relations, an d in-place reprogramming without replacement and rewiring. The tool optimis es the combinational component of the configurable logic blocks (CLBs) afte r layout, and does not necessitate any rerouting or rewiring. Hence, delay and CLB usage are left unchanged, while power is minimised. As the algorith m operates locally on the various LUT clusters of the network, it is applic able and best performs on large examples as demonstrated by our experimenta l results: an average power reduction of 11.5% has been obtained on standar d benchmark circuits.