Methods of exploiting simulation technology for simulating the timing of dynamically reconfigurable logic

In a dynamically reconfigurable design, the logic on the FPGA changes over time. The operation of each distinct combination of circuits that can be ac tive on a device simultaneously must be functionally verified. The dynamic transitions between different circuit combinations must also be functionall y verified. After successful verification, a unique floorplan must be creat ed for each of the circuit combinations by the physical design tools. The d etailed timing information derived for each floorplan must be back-annotate d and the circuit combinations must be individually reverified with the acc urate timing information. The physical design tools must place and route dy namically reconfigurable circuits that share common areas of the device arr ay. A technique for functionally verifying dynamically reconfigurable desig ns, called Dynamic Circuit Switching (DCS), has been reported previously. T he paper presents new techniques that make the simulation of dynamically re configurable logic with back-annotated timing possible for the first time. It also describes DCSTech, a CAD tool that automates these techniques. DCST ech works in conjunction with an enhanced version of DCS, called DCSim. The new design techniques provide the core of a design flow for dynamically re configurable logic. The new CAD tools, together with others reported previo usly, constitute an emerging CAD framework that automates the new design fl ow.