High-performance embedded SOI DRAM architecture for the low-power supply

This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM, The degradation o f the transistor performance caused by boosted wordline voltage level is di stinctly apparent in the low voltage range, In our proposed stressless SOT DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can be relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor c an be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteri stics can be improved. Secondly, we propose the body-bias-controlled SOI-ci rcuit architecture which enhances the performance of the logic circuit at s ub-1.2-V power supply voltage. Experimental results verify that the propose d circuit architecture has the potential to reduce the gate-delay time up t o 30% compared to the conventional one. This proposed architecture could pr ovide high performance in the low-voltage embedded SOI DRAM.