This paper describes the influence of the process fluctuations such as the
critical dimension (CD) variation upon the interconnect capacitance C and R
C delay. It is found that there is a tradeoff between C and RC delay variat
ions because of the fringing capacitance. An interconnect design guideline
to reduce C and/or RC delay variations is proposed, Also, C and RC delay va
riations for Cu interconnect are discussed.