Embedded checker architectures for cyclic and low-cost arithmetic codes

Code checkers that monitor the outputs of a system can detect both permanen t and transient faults. We present two novel architectures of embedded self -testing checkers for low-cost and cyclic arithmetic codes, one based on co de word generators and adders, the other based on code word accumulators. I n these schemes, the code checker receives all possible code words but one, irrespective of the number of different code words that are produced by th e circuit under check (CUC). So any code checker can be employed that is se lf-testing for all or a particular subset of code words, and the structure of the code checker need not be tailored to the set of code words produced by the CUC. The proposed code word generators and accumulators are built fr om simple standard hardware structures, counters and end-around-carry adder s. They can also be utilized in an off-line BIST environment as pattern gen erators and test response compactors.