nu MOS-based sorter for arithmetic applications

The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In pa rticular, both an (8 x 8)-multiplier and a (15,4) counter which use a sorte r as the main building block have been implemented. Traditional disadvantag es of binary sorters such as their hardware intensive nature are avoided by using vMOS circuits. It allows both an improving of previous results for m ultipliers based on a similar architecture, and to obtain a new type of cou nter which shows a reduced delay when compared to a conventional implementa tion.