New self-dual circuits for error detection and testing

In this paper new methods for the transformation of a given combinational c ircuit into a self-dual circuit based on the notion of a self-dual compleme nt are investigated. The large variety of self-dual complements can be util ized to optimize the transformed self-dual circuit. Self-dual duplication a nd self-dual parity prediction are considered in detail. As a method for th e reduction of self-dual outputs, output space compaction of self-dual outp uts is considered. For the first time we also describe in this paper how a self-dual circuit can be modified into a self-dual fault-secure circuit.