Self-checking synchronous FSM network design with low overhead

A method of a self-checking synchronous Finite State Machine (FSM) network design with low overhead is developed. Checkers are used only for FSMs, whi ch output lines are at the same time output lines of the network. The check ers observe output lines of these FSMs. The method is based on reducing the problem to a self-checking synchronous FSM design. The latter is provided by applying a special description of FSM namely, so-called unate Programmab le Logic Array (PLA(u)) description. Single stuck-at fault on the FSM poles and gate poles are considered. PLA(u) realization of FSM allows a factoriz ed or multilevel logic synthesis. They both provide a unidirectional manife station of the above mentioned faults on the output lines of the correspond ing FSMs. This realization also gives rise to a transparency of each compon ent FSM of the network for the faults. PLA(u) realization is derived from t he State Transition Graph (STG) description of FSMs with using the m-out-of -n encoding of its states and insignificant expanding the products of STG. The problem of replacing an arbitrary synchronous FSM network for the self- checking one with low overhead is discussed.