The authors describe an efficient method for designing current-mode group-d
elay equalisers, The method is based on introducing zeros into the right-ha
nd s-plane by mirroring the Doles of an LC ladder network. This is achieved
by developing a current-mode model capable of implementing the pole-zero m
irroring technique. Using multiple-output OTAs and grounded capacitors, the
model is used to derive an nth-order active group-delay equaliser structur
e which is simpler, has better correction accuracy and is less sensitive wh
en compared to cascade approach based equalisers. The equaliser design invo
lves two optimisation algorithms. The first algorithm generates a polynomia
l function whose group-delay response equalises the filter response. The se
cond algorithm produces the equaliser component values as a result of solvi
ng a set of nonlinear equations generated from coefficient matching the equ
aliser transfer function to the polynomial generated from the first algorit
hm. Simulated results with CMOS OTAs and measured results based on discrete
realisation of a 6th-order equaliser are included. The results demonstrate
that the equaliser can effectively compensate the delay characteristics of
a 7th-order 5.75MHz lowpass elliptic video filter to < 5 ns ripple over 90
% of the filter passband.