An on-chip clock-adjusting circuit with sub-100-ps resolution for a high-speed DRAM interface

A novel fully digital fine-delay circuit for a high-speed DRAM interface is proposed. The circuit consists of arrayed delay components and generates a group of rail-to-rail delayed signals with sub-100-ps resolution, The inpu t-coupling element (squeezer) in the delay component converges the variatio ns of the resolution. A test device design using 0.35-mu m technology demon strates that a resolution of 26 ps can be achieved, A clock-recovery circui t using this circuit has a two-clock-cycle lock time and sub-100-ps error.