Self-timed carry-lookahead adders

Integer addition is one of the most important operations in digital compute r systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a self-timed carry-looka head adder in which the logic complexity is a linear function of n, the num ber of inputs, and the average computation time is proportional to the loga rithm of the logarithm of n. To the best of our knowledge, our adder has th e best area-time efficiency which is Theta(n log log n). An economic implem entation of this adder in CMOS technology is also presented. SPICE simulati on results show that, based on random inputs, our 32-bit self-timed carry-l ookahead adder is 2.39 and 1.42 times faster than its synchronous counterpa rt and self-timed ripple-carry adder, respectively; and, based on statistic al data gathered from a 32-bit ARM simulator, it is 1.99 and 1.83 times fas ter than its synchronous counterpart and self-timed ripple-carry adder, res pectively.