Integer multiplication with overflow detection or saturation

High-speed multiplication is frequently used in general-purpose and applica tion-specific computer systems. These systems often support integer multipl ication, where two n-bit integers are multiplied to produce a 2n-bit produc t. To prevent growth in word length, processors typically return the n leas t significant bits of the product and a flag that indicates whether or not overflow has occurred. Alternatively, some processors saturate results that overflow to the most positive or most negative representable number. This paper presents efficient methods for performing unsigned or two's complemen t integer multiplication with overflow detection or saturation. These metho ds have significantly less area and delay than conventional methods for int eger multiplication with overflow detection or saturation.