Simulation of dopant redistribution during gate oxidation including transient-enhanced diffusion caused by implantation damage

Citation
T. Uchida et al., Simulation of dopant redistribution during gate oxidation including transient-enhanced diffusion caused by implantation damage, JPN J A P 1, 39(5A), 2000, pp. 2565-2576
Citations number
20
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science
Volume
39
Issue
5A
Year of publication
2000
Pages
2565 - 2576
Database
ISI
SICI code
Abstract
Dopant redistribution during gate oxidation in metal-oxide-semiconductor (M OS) fabrication processes has been studied by secondary-ion mass spectromet ry (SIMS). In the first set of experiments, dopant profiles after gate oxid ation are measured and compared to those after N-2 annealing. From the meas ured profiles, the contribution of oxidation-enhanced diffusion (OED) to th e entire dopant redistribution is determined and an OED model parameter is calibrated. In the second set of experiments, samples which are subjected o nly to wafer loading and unloading steps are prepared and dopant profiles a re measured. From the measured profiles, the magnitude of transient-enhance d diffusion (TED) which occurs during the wafer loading step is estimated a nd an interstitial-clustering parameter is calibrated. The parameters calib rated in this study are combined with the point-defect parameters taken fro m the literature, and dopant redistribution during the entire gate oxidatio n cycle is simulated. Calculated dopant profiles agree well with the measur ed SIMS profiles and show correct time dependence of TED and OED, as observ ed in the present experiments. In the simulations, interstitial concentrati on at the oxidizing Si/SiO2 interface is found to be 40 times the equilibri um concentration. The supersaturation caused by surface oxidation is small and the contribution of OED is negligible under typical gate oxidation cond itions where oxide thickness is less than 100 Angstrom. Dopant profiles aft er gate oxidation are mainly dominated by TED. However, as oxidation procee ds, the contribution of OED increases because it continues while TED almost ends in the wafer loading step of gate oxidation. Segregation of boron in the channel region is also studied. It is found that a greater amount of bo ron is lost in oxidation than in N-2 annealing. The effect of segregation o n device characteristics is not negligible for buried-channel PMOS devices, because the threshold voltage of the devices is sensitive to the change in the amount of boron.