Study of an elevated drain fabrication method for ultra-shallow junction

Citation
M. Nakano et al., Study of an elevated drain fabrication method for ultra-shallow junction, JPN J A P 1, 39(4B), 2000, pp. 2155-2157
Citations number
11
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science
Volume
39
Issue
4B
Year of publication
2000
Pages
2155 - 2157
Database
ISI
SICI code
Abstract
An elevated diffusion layer fabricated from polycrystalline silicon (poly-S i) by solid phase diffusion was investigated in detail by secondary-ion mas s spectroscopy (SIMS) analysis. We clarified that it was necessary to contr ol the native oxide in the poly-Si/Si substrate interface and use small-gra ined poly-Si to fabricate uniform and controllable shallow junctions. The l ow-capacitance sidewall-elevated drain (LCSED) metal oxide semiconductor fi eld-effect transistor (MOSFET) fabricated by the oxygen-free load-lock low- pressure chemical vapor deposition (LPCVD) poly-Si (L/L poly-Si) was extrem ely effective for marked scaling down of transistor size and realizing an u ltra low reversed junction leakage current.