A low thermal budget high performance 0.25-0.18 mu m merged logic device and dynamic random access memory application

Merged dynamic random access memory (DRAM) with logic technology has been w idely investigated because of to its high on-chip memory bandwidth, low pow er consumption, customized memory size, and small footprint advantages. A l ow thermal budget 0.25-0.18 mu m embedded DRAM technology has been develope d to merge a high-performance logic device and high-density DRAM on the sam e chip. In this newly developed technology, shallow trench isolation, a tri ple well, TiSix polycide, titanium salicide, a self-aligned contact poly-vi a and a low thermal budget oxide-nitride-oxide (ONO) as well as Ta2O5 capac itor dielectrics used for 1 Gbit DRAM design, are being applied. A 32 Mbit synchronous DRAM macro was designed based on this technology and is propose d offered as a drop-in module for embedded DRAM applications.