Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips

This paper discusses the electrostatic discharge (ESD) robustness in silico n-on-insulator (SOI) high-pin-count high-performance semiconductor chips. T he ESD results demonstrate that sufficient ESD protection levels are achiev able in SOI microprocessors using lateral ESD SOI polysilicon-bound gated d iodes without the need for additional masking steps, process implants or ES D design area. (C) 2000 Elsevier Science B.V. All rights reserved.