Chained backplane communication architecture for scalable multiprocessor systems

A scalable backplane topology which allows a practically unlimited number o f modules with identical interfaces is presented. Short, buffered, point-to -point connections overcome clock skew problems. Synchronized, pipelined da ta transfer operations ensure high throughput and reasonably low latency ti mes for fine-grain parallel algorithms. A simple bus interface logic withou t any special hardware configuration guarantees a cheap implementation with standard FPGAs. The measured performance in our FPGA based prototype with 32 bit wide data bus shows a throughput of 160 Mbytes/s for each module wit h 75 us latency time between modules. (C) 2000 Elsevier Science B.V. All ri ghts reserved.