A COMPLEMENTARY PAIR OF 4-TERMINAL SILICON SYNAPSES

We have developed a complementary pair of pFET and nFET floating-gate silicon MOS transistors for analog learning applications. The memory s torage is nonvolatile; hot-electron injection and electron tunneling p ermit bidirectional memory updates. Because these updates depend on bo th the stored memory value and the transistor terminal voltages, the s ynapses can implement a learning function. We have derived a memory-up date rule for both devices, and have shown that the synapse learning f ollows a simple power law. Unlike conventional EEPROMs, the synapses a llow simultaneous memory reading and writing. Synapse transistor array s can therefore compute both the array output, and local memory update s, in parallel. We have fabricated prototype synaptic arrays; because the tunneling and injection processes are exponential in the transisto r terminal voltages, the write and erase isolation between array synap ses is better than 0.01%. The synapses are small, and typically are op erated at subthreshold current levels; they will permit the developmen t of dense, low-power silicon learning systems.