Low-power, small-footprint gigabit Ethernet-compatible optical receiver circuit in 0.25 mu m CMOS

Experimental results for a gigabit Ethernet-compatible photoreceiver circui t generating CMOS logic level are presented. A single-ended preamplifier is combined with a multi-stage differential postamplifier with inverse scalin g to increase bandwidth. Circuits are realised in 0.25 mu m CMOS, dissipati ng 26mW or less. The analogue portion of the receiver operates at 2 mu A av erage input current at 1.25Gbit/s, increasing to similar to 10 mu m when CM OS levels are generated. A maximum speed of 2.1Gbit/s is reported for the a nalogue portion.