Architectures and synthesis algorithms for power-efficient bus interfaces

In this paper; we present algorithms for the synthesis of encoding and deco ding interface logic that minimizes the average number of transitions on he avily-loaded global bus lines at no cost in communication throughput (i.e., one word is transmitted at each cycle). The distinguishing feature of our approach is that it does not rely on designer's intuition, but it automatic ally constructs low-transition activity codes and hardware implementation o f encoders and decoders, given information on word-level statistics. We pro pose an accurate method that is applicable to low-width buses, as well as a pproximate methods that scale well with bus width. Furthermore, we introduc e an adaptive architecture that automatically adjusts encoding, to reduce t ransition activity on buses whose word-level statistics are not known a pri ori. Experimental results demonstrate that our approaches well out-perform specialized low-power encoding schemes presented in the past.