Generating synthetic benchmark circuits for evaluating CAD tools

For the development and evaluation of computer-aided design tools fur parti tioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is req uired. Observing the lack of industrial benchmark circuits available for us e in evaluation tools, one could consider to actually generate synthetic ci rcuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component li brary, together with the restriction that no combinational loops are introd uced, now broadens the scope to timing-driven and logic optimizer applicati ons. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuit s is hardly influenced by the suggested extensions and that the resulting c ircuits are more realistic than before. An indirect validation verifies tha t existing partitioning programs have comparable behavior for both real and synthetic circuits, The problems of accounting for timing-aware characteri stics in synthetic benchmarks are addressed in detail and suggestions for e xtensions are included.