Synthesis of symmetric functions for path-delay fault testability

A new technique of synthesizing totally symmetric Boolean functions is pres ented that achieves complete robust path-delay fault testability. We show t hat every consecutive symmetric function can be expressed as a logical comp osition (e.g., AND, NOR) of two unate symmetric functions, and the resultin g composite circuit can be made robustly path-delay fault testable, if the constituent unate functions are synthesized as two-level irredundant circui ts. Nonconsecutive symmetric functions can also be synthesized by decomposi ng them into a set of consecutive symmetric functions. The circuit cost of the proposed design can further be reduced by a novel algebraic factorizati on technique based on some combinatorial clues. The overall synthesis guara ntees complete robust path-delay fault testability and can be completed in linear time. The results shows that the proposed method ensures a significa nt reduction in hardware, as well as in the number of paths,,which in turn, reduces testing time, as compared to those of the best-known earlier metho ds.