Clock-delayed (CD) domino is a self-timed dynamic logic family developed to
provide single-rail gates with inverting or noninverting outputs. CD domin
o is a complete logic family and is as easy to design with as static CMOS c
ircuits from a logic design and synthesis perspective. Design toots develop
ed for static CMOS are used as part of a methodology for automating the des
ign of CD domino circuits. The methodology and CD domino's characteristics
are demonstrated in the design of a 32-b carry look-ahead adder. The adder
was fabricated with MOSIS's 0.8 mu m CMOS process with scalable CMOS design
rules that allow a 1.0-mu m drawn gate length. Measurements of the adder s
how a worst case addition of 2.1 ns. The CD domino adder is 1.6X faster tha
n a dual-rail domino adder designed with the same cell library and technolo
gy.