Clocked CMOS adiabatic logic with integrated single-phase power-clock supply

The design and experimental evaluation of a clocked adiabatic logic (CAL) i s described in this paper. CAL is a dual-rail logic that operates from a si ngle-phase ac power-clock supply. This new low energy logic makes it possib le to integrate all power control circuitry on the chip, resulting in bette r system efficiency, lower cost, and simpler power distribution. CAL can al so be operated from a de power supply in a nonenergy-recovery mode compatib le with standard CMOS logic. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small ext ernal inductor between the chip and a low-voltage de supply. Circuit operation and performance are evaluated using a chain of inverters realized in a 1.2 mu m CMOS technology Experimental results show that energ y savings are achieved at clack frequencies up to about 40 MHz as compared to the nonadiabatic mode. Since CAL can operate both in adiabstic and nonad iabatic modes, power management strategies may be based upon switching betw een modes when necessary.