Advanced process/device modeling and its impact on the CMOS design solution

This paper reports the application results of the state-of-the-art advanced process/device modeling to the 0.13 [mu m] CMOS design solution. It has be en demonstrated that the S/D-extension junction depth, the well profile, th e channel profile and the drive current of the 0.13 [mu m] CMOS can be pred icted with reasonable accuracy. Further model improvement is required to pr edict the at and the Vt-Lg characteristics of the devices with the tilted p ocket I/I more accurately. It is quite beneficial to construct several desi gn maps by using the state-of-the-art advanced TCAD in a 'carpet bombing' w ay in the early stage of the development of new generation CMOS.