An advancing front meshing algorithm using NURBS for semiconductor processsimulation

A surface extraction algorithm with NURBS has been developed for the mesh g eneration from the scattered data after a cell-based simulation. The triang ulation of a surface is initiated with a step of describing the geometry al ong the polygonal boundary with multiple points. In this work, an NURBS sur face can be generated with scattered data for each polygonal surface by emp loying a multilevel B-spline surface approximation. The NURBS mesh in accor dance with our algorithm excellently represents the surface evolution of th e topography on the wafer. A dynamically allocated topography model, so-cal led cell advancing model, is proposed to resolve an extensive memory requir ement for the numerical simulation of a, complicated structure on the wafer . A concave cylindrical DRAM cell capacitor was chosen to test the capabili ty of our model. A set of capacitance present in the cell capacitor and int erconnects was calculated with three-dimensional tetrahedral meshes generat ed from the NURBS surface on GRAY T3E supercomputer. A total of 5,475,600 ( 130 x 156 x 270) cells was employed for the simulation of semiconductor reg ions comprising four DRAM cell capacitors with a dimension of 1.3 mu m x 1. 56 mu m x 2.7 mu m. The size of the required memory is about 22 Mbytes and the simulation time is 64,082 seconds. The number of nodes for the FEM calc ulation was 70,078 with 395,064 tetrahedrons.