A new FPGA architecture for high performance bit-serial pipeline datapath

In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel s ystems require large amount of routing resource which is especially critica l in using FPGAs. Their device utilization and operation frequency become l ow because of large routing penalty. Whereas bit-serial circuits are very e fficient in routing, therefore are able to achieve a very high logic utiliz ation. Our proposed FPGA architecture is designed taking into account the s tructure of bit-serial circuits to optimize the logic and routing architect ure. Our FPGA guarantees near 100% logic utilization with a straightforward place and route tool due to high routability of bit-serial circuits and si mple routing interconnect architecture. The FPGA chip core which we designe d consists of around 200k transistors on 3.5 mm square substrate using 0.5 mu m a-metal CMOS process technology.