A 3 V low power 156/622/1244 Mbps CMOS parallel clock and data recovery circuit for optical communications

This paper presents the implementation of a 3 V low power multi-rate of 156 , 622, and 1244 Mps clock and data recovery circuit (CDR) for optical commu nications tranceiver using new parallel clock recovery architecture based o n dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical syst em uses the method that compares the input data. with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one -eighth frequency of the input data signal. Moreover, since the circuit wor ks at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this reco very circuit can work with power dissipation of less than 40mW with a singl e 3 V supply. All the simulations are based on HYUNDAI 0.65 mu m N-Well CMO S double-poly double-metal technology.