Electrothermal modelling of GaAs MESFETs

In this paper a new analytic electrothermal model of a GaAs FET is proposed in order to evaluate the thermal field in the semiconductor body for an ea sy, fast and reliable layout design using a personal computer. The contribu tion to the thermal resistance of all the top and bottom layers of a typica l chip and the interaction of the channel temperature with the drain curren t are taken into account. A comparison with a three-dimensional finite-diff erence simulator and experimental data confirms the accuracy of the model. The CAD tool in which the mathematical model has been implemented can be us ed for the layout design since it is able to calculate the optimal spacing between contiguous devices to minimize the mutual thermal coupling and also the optimal number of gate fingers and gate-to-gate spacing of a single po wer device with a multigate layout. The proposed technique is general and c an be applied to silicon as well as to heterojunction FET devices.