Research on applying direct plating to additive process for printed circuit board

Citation
Yy. Chiang et al., Research on applying direct plating to additive process for printed circuit board, J ELEC MAT, 29(8), 2000, pp. 1001-1006
Citations number
6
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science
Journal title
JOURNAL OF ELECTRONIC MATERIALS
ISSN journal
03615235 → ACNP
Volume
29
Issue
8
Year of publication
2000
Pages
1001 - 1006
Database
ISI
SICI code
0361-5235(200008)29:8<1001:ROADPT>2.0.ZU;2-E
Abstract
The feasibility of applying direct-metallization as an additive process for printed circuit board was explored. Pd/Sn catalyst was used in the activat ion step and the content of Pd adsorption was found to be the controlling f actor. The Pd content was affected by the conditions of various steps inclu ding condition, activation, acceleration, and promotion. The sequence of ap plying photoresist and activation with Pd/Sn catalyst plus promotion with N a2S solution was also studied. It was found that a well-defined pattern cou ld be obtained by applying the Pd/Sn catalyst layer before applying the pho to-resist film. If the photoresist was applied before the activation step, copper deposition tended to develop beyond the desired pattern region on th e surface. We also found that the lateral growth rate of copper deposition was inversely affected by the concentration of copper sulfate. This can be explained by a deposition model in which the lateral growth of copper depos ition is caused by the charge transfer of the sulfur atom as a bridging lig and.